The present invention relates to a semiconductor memory device consisting of a synchronous RAM (Random Access Memory) which is used in a semiconductor memory device consisting of a synchronous RAM and, more particularly, is capable of simultaneously performing write access of the same data at an arbitrary address and read access of a plurality of data.
FIG. 4 is a block diagram showing a main part of a conventional semiconductor memory device consisting of a synchronous RAM.
The conventional semiconductor memory device includes a one-port RAM 49, a selector 48 for selectively inputting an address, a serial/parallel converter 50 for serial/parallel-converting an output from the RAM 49, a data input terminal 41 for inputting input data DI, a read/write terminal 42 for inputting an R/W (read/write) control signal R/W, a clock terminal 43 for inputting a clock signal CLK, a read address terminal 44 for inputting a read address RADD(N) where N is a positive integer of 2 or more, a read address terminal 45 for inputting a read address RADD(N-1), a write address terminal 46 for inputting a write address WADD, an address select terminal 47 for inputting an address select signal SEL, a data output terminal (N) 51 for outputting output data DO(N), a data output terminal (N-1) 52 for outputting output data DO(N-1), and a data output terminal (N-2) 53 for outputting output data DO(N-2).
An operation of the conventional semiconductor memory device will be described below with reference to operation timing charts shown in FIGS. 5A to 5G. Note that, for descriptive simplicity, FIGS. 5A to 5G show a case wherein a condition N=2 is satisfied.
As shown in FIG. 4, when data at N different addresses are to be simultaneously extracted by a one-port RAM within one time slot, the following operation is performed. That is, as shown in FIG. 5D, a clock signal CLK having a frequency of (N+1) times is input to the one-port RAM 49 within one time slot of input data in FIG. 5A, and even-numbered periods of the clock signal CLK are assigned to a read control signal as shown in FIG. 5B. As shown in FIG. 5C, N multi-addresses switched by the selector 48 are accessed, data output and controlled in a sequence [Read (N), Read (N-1),..., Write]as shown in FIG. 5E is serial/parallel-converted by the serial/parallel converter 50, and as shown in FIGS. 5F and 5G, output data DO(N), DO(N-1),... are distributively output. Input data A and B shown in FIG. 5A are written at the period of the last clock signal CLK within one time slot in accordance with the control signal of FIG. 5B.
As described above, when an arrangement uses the conventional one-port RAM shown in FIG. 4, and data at N different addresses are to be simultaneously extracted within one time slot, a clock signal having a frequency of (N+1) times must be input to the one-port RAM within one time slot. When the frequency of the clock signal is increased, the RAM may not be operated, or a high-performance RAM is required. Therefore, the yield of LSIs is disadvantageously decreased.